1. Technical Field of the Invention
The invention relates generally to communication systems; and, more particularly, it relates to encoding and decoding signals employed within such communication systems.
2. Description of Related Art
Data communication systems have been under continual development for many years. One such type of communication system that continues to be of significant interest is that which employs iterative error correction codes. Of particular interest is a communication system that employs LDPC (Low Density Parity Check) code. Communications systems with iterative codes are often able to achieve lower BER (Bit Error Rate) than alternative codes for a given SNR (Signal to Noise Ratio).
The use of LDPC coded signals continues to be explored within many newer application areas. Some examples of possible communication systems that may employ LDPC coded signals include communication systems employing 4 wire twisted pair cables for high speed Ethernet applications (e.g., 10 Gbps (Giga-bits per second) Ethernet operation according to the IEEE 802.3an (10 GBASE-T) emerging standard) as well as communication systems operating within a wireless context (e.g., in the IEEE 802.11 context space including the IEEE 802.11n emerging standard). In general, LDPC coding can be applied to any type of communication system in which data is sent from one place to another where error correction capability is desired.
For any of these particular communication system application areas, near-capacity achieving error correction codes are very desirable. The latency constraints, which would be involved by using traditional concatenated codes, simply preclude their use in such applications in very high data rate communication system application areas.
When performing processing of such LDPC signals within communication systems, a designer has quite a degree of freedom by which to implement the hardware to perform such encoding and/or decoding processing. However, in many communication systems, such as wireless LAN and satellite communication system, multiple error correcting codes each possible having different block sizes and different code rates are oftentimes needed. For example, a typical prior art approach is to design and construct multiple LDPC codes to accommodate each of the different block sizes and code rates required for the particular communication system application. For example, in IEEE 802.11n Joint Proposal (depicted further below using reference [d]), twelve (12) distinct codes are constructed for four (4) different code rates. Each code rate has three (3) different block sizes, and every block size has its own code structure. Currently, the typical approach in the art is to employ separate and distinct functional blocks and/or circuitry portions within a communication device to perform the appropriate processing for each of these different LDPC codes. This approach inherently requires more hardware in implementation. In other words, within communication devices that seek to operate on a variety of LDPC codes (i.e., variable code rate and/or modulation type communication devices), the typical design approach is to provision separate functional blocks and/or circuitry for each of the separate LDPC codes which are to be processed.
This can prove to be very expensive in terms of a variety of cost factors including real estate, actual dollar cost, and complexity in terms of the number of gates required within the communication device. With the continual advent of communication devices and communication systems being designed to accommodate multi-code types signals (including multi-code rate and/or multi-modulation types signals whose code rate and/or modulation can vary as frequently as on a symbol by symbol or frame by frame basis), there continues to be a need in the art for better and more efficient LDPC code design as well as the associated hardware that is designed and implemented to support such LDPC codes.
In the art of communication systems and communication devices that employ multiple LDPC code signals, shortening and puncturing can be performed to generate the various LDPC coded signals. However, using the prior art approaches of shortening and puncturing, the LDPC codes resulting there from inherently require the multiple functional block and/or circuitry approach to hardware design, in that, each of the resulting LDPC codes have a different code structure. In addition, many of the prior art approaches to shortening and puncturing require a particular shortening and puncturing ratio which also inherently narrows the type of LDPC codes which can be selected and designed while still complying with those particular shortening and puncturing approaches.
The following 5 references describe some prior art approaches to multiple LDPC code design, some of which employ prior art approaches to shortening and puncturing.
[a] PHY Advanced Coding “ad hoc” team, “Motion JP-K043: Low-Density Parity Check (LDPC) Code and Encoding Procedure Definition,” 7 pages.
[b] Motorola, “Column weight distribution,” Nov. 15, 2005, 5 pages.
[c] Huaning Niu and Chiu Ngo, Samsung, “Performance evaluation of different shortening schemes puncturing patens,” Nov. 29, 2005, 23 pages.
[d] Syed Aon Mujtaba, Agere Systems Inc., “TGn Sync Proposal Technical Specification,” doc.: IEEE 802.11-04/0889r7, IEEE P802.11 Wireless LANs, 133 pages.
[e] Michael Livshits, Nortel Networks Limited, “Shortening and puncturing performance analysis,” Dec. 7, 2005, 4 pages.